The invention relates to a vertical-type double diffused MOSFET and a method of fabricating the same.
FIGS. 1A to 1D illustrate conventional fabrication processes of a vertical-type double diffused MOSFET. In FIG. 1A, a n.sup.- -type epitaxial layer 2 is formed on a silicon substrate 1. The n.sup.- -type epitaxial layer 2 is subjected to a thermal oxidization to form an oxide silicon film 17 having a thickness in the range from 600 to 1000 nm. Subsequently, openings are formed in a peripheral area B opposite to an element formation area A by use of photolithography. The openings are subjected to an ion-implantation and a heat treatment to form a p-type well region 5, after which a surface of the p-type well region 5 is subjected to a thermal oxidization to form an oxide silicon film 18 having a thickness in the range from 400 to 600 nm. Subsequently, both a part of the oxide silicon film 18 and the oxide silicon film 17 are removed by use of photolithography. Further, a gate oxide film 7a is formed by use of a thermal oxidization on the element formation area A in which oxide silicon films 17 and 18 have been removed. At this time, the remaining oxide silicon film 18 is also subjected to a thermal oxidization to be made into a field oxide film 6a as shown in FIG. 1B.
In FIG. 1C, a polycrystalline silicon film 8 is deposited on an entire surface of the oxide films 7a and 6a, followed by patterning, so that the polycrystalline silicon film 8 may serve as a mask. An ion-implantation of boron of a concentration in the range from 6.times.10.sup.13 to 14.times.10.sup.13 cm.sup.-2 is carried out by use of the mask, followed by a heat treatment to form p-type base regions 9.
In FIG. 1D, an ion-implantation is carried out by use of the polycrystalline silicon film 8 as the mask, followed by a heat treatment so that a n.sup.+ -type source region 10 is formed in the p-type base region 9. Further, an ion-implantation is carried out by use of a photoresist film as a mask, followed by a heat treatment to form a p.sup.+ -type back gate region 11 in the n.sup.+ -type source region 10. After that, an insulation layer 12 is deposited, followed by opening to form a source electrode 13 and a gate electrode 14. Further, a drain electrode is formed.
A conventional vertical-type double diffused MOSFET fabricated by the set forth processes is engaged with following disadvantage. FIGS. 2 and 3 illustrate two types of structures of the gate oxide film 7a and the field oxide film 6a in which the gate oxide film 7a overlays an edge portion of the p-type well region 5 in order to reduce a higher electric field so that the p-type base regions 9 take the same potential each other.
First, when openings of the photoresist film for the p-type well region 9 and openings of the photoresist film for the gate oxide film 7a overlap each other, a structure of oxide films shown in FIG. 2 is formed. Such a structure of the oxide films comprises a field oxide film 6a, a field oxide film 6b and a gate oxide film 7b. When the oxide silicon film 17 is etched to form the gate oxide film 7a, the photoresist film which overlays the field oxide film and an edge portion of the silicon oxide film 17 is so used as a mask that the edge portion of the silicon oxide film 17 remains. A thermal oxidization for the gate oxide film formation subjects the remaining edge portion of the silicon oxide film 17 to re-oxidization to form the field oxide film 6b. The field oxide film 6b provides a large difference in level thereby resulting in an undesirable definition of the polycrystalline silicon film 8 to be formed on the oxide films. The gate electrode, thus, has a variable high resistance.
Second, when there is no overlapping of openings of the photoresist film used for forming the p-type well region 9 and openings of the photoresist film used for forming the gate oxide film 7a, a structure of oxide films shown in FIG. 3 is formed. In this case, when the oxide silicon film 17 is etched to form the gate oxide film 7a, the photoresist film serving as a mask overlays the oxide film 18 only. Consequently, no field oxide film 6b is formed. A structure shown in FIG. 3 is not associated with a problem such as an undesirable definition of the polycrystalline silicon film 8 to be formed on the oxide films. The structure shown in FIG. 3 is, however, engaged with other problems such as a formation of a crystal defect. The ion-implantation and the heat treatment carried out for forming the n-type well region produces many crystal defects in an overlaid area C of the well region 5 with the gate oxide film 7a. Consequently, an overlaying area of the gate oxide film 7a also has a high concentration of crystal defects which causes a gate short.